1. Field of the Invention
This invention relates to HDLC (High Level Data Link Control) formatters. More particularly, the invention concerns a high speed multi-port serial-to-PCI bus interface for an HDLC formatter that allows messages carried over a data link to be rapidly transferred into and out of a message processing core.
2. Description of the Prior Art
In HDLC processing for signaling applications, such as telephone network control messaging, messages to be processed arrive on a serial link and are transferred over a PCI bus via DMA channeling to a message processing area having an external RAM and a message processing core. In the past, the speed at which message processing could be performed has been limited by slow message throughput from the serial data stream into the messaging area, and visa-versa.
The problem is that PCI/DMA data exchange between the serial side of the HDLC formatter and the message processing core has required considerable handshaking to coordinate RAM read and write operations for messages moving in the Transmit (TX) and Receive (RCV) directions. For this reason, message processing support has conventionally been limited to a single serial link per HDLC formatter providing only a modest number (e.g., 32) of message processing channels (one per serial link timeslot).
Accordingly, there is a need in the art for an improved serial-to-PCI bus interface in an HDLC formatter used for message processing signaling applications. What is required is an improved multi-port serial-to-PCI bus interface that provides rapid PCI/DMA data exchange so as to allow the HDLC formatter to handle multiple serial links with multiple message-carrying timeslots for high bandwidth messaging.